//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

.const .align 16 .b8 params[384];

.visible .func  (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
	.param .b32 __direct_callable__oxMain_param_0,
	.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
)
{
	.reg .pred 	%p<12>;
	.reg .b16 	%rs<41>;
	.reg .f32 	%f<123>;
	.reg .b32 	%r<24>;
	.reg .b64 	%rd<49>;


	ld.param.u32 	%r2, [__direct_callable__oxMain_param_0];
	ld.param.f32 	%f29, [__direct_callable__oxMain_param_1+4];
	ld.param.f32 	%f28, [__direct_callable__oxMain_param_1];
	ld.const.u64 	%rd8, [params+56];
	cvta.to.global.u64 	%rd9, %rd8;
	mul.wide.s32 	%rd10, %r2, 4;
	add.s64 	%rd11, %rd9, %rd10;
	ld.global.u32 	%r3, [%rd11];
	setp.ne.s32 	%p1, %r3, 0;
	and.b32  	%r4, %r3, 1;
	setp.eq.b32 	%p2, %r4, 1;
	not.pred 	%p3, %p2;
	mov.f32 	%f117, 0f00000000;
	and.pred  	%p4, %p1, %p3;
	mov.f32 	%f118, %f117;
	mov.f32 	%f119, %f117;
	mov.f32 	%f120, %f117;
	mov.f32 	%f121, %f117;
	mov.f32 	%f113, %f117;
	@%p4 bra 	$L__BB0_11;

	ld.const.u64 	%rd12, [params+8];
	cvta.to.global.u64 	%rd13, %rd12;
	mul.wide.u32 	%rd14, %r2, 12;
	add.s64 	%rd15, %rd13, %rd14;
	ld.global.s32 	%rd1, [%rd15];
	ld.global.s32 	%rd2, [%rd15+4];
	ld.global.s32 	%rd3, [%rd15+8];
	ld.const.u32 	%r1, [params+16];
	setp.gt.u32 	%p5, %r1, %r2;
	@%p5 bra 	$L__BB0_3;
	bra.uni 	$L__BB0_2;

$L__BB0_3:
	mov.f32 	%f113, 0f3F800000;
	bra.uni 	$L__BB0_4;

$L__BB0_2:
	sub.s32 	%r5, %r2, %r1;
	ld.const.v2.u64 	{%rd16, %rd17}, [params+32];
	cvta.to.global.u64 	%rd20, %rd16;
	mul.wide.u32 	%rd21, %r5, 4;
	add.s64 	%rd22, %rd20, %rd21;
	ld.const.u64 	%rd23, [params+24];
	cvta.to.global.u64 	%rd24, %rd23;
	shl.b64 	%rd25, %rd1, 3;
	add.s64 	%rd26, %rd24, %rd25;
	ld.global.v2.f32 	{%f36, %f37}, [%rd26];
	shl.b64 	%rd27, %rd2, 3;
	add.s64 	%rd28, %rd24, %rd27;
	ld.global.v2.f32 	{%f40, %f41}, [%rd28];
	shl.b64 	%rd29, %rd3, 3;
	add.s64 	%rd30, %rd24, %rd29;
	ld.global.v2.f32 	{%f44, %f45}, [%rd30];
	mov.f32 	%f48, 0f3F800000;
	sub.f32 	%f49, %f48, %f28;
	sub.f32 	%f50, %f49, %f29;
	mul.f32 	%f51, %f28, %f40;
	mul.f32 	%f52, %f28, %f41;
	fma.rn.f32 	%f53, %f50, %f36, %f51;
	fma.rn.f32 	%f54, %f50, %f37, %f52;
	fma.rn.f32 	%f55, %f29, %f44, %f53;
	fma.rn.f32 	%f56, %f29, %f45, %f54;
	abs.f32 	%f57, %f55;
	cvt.rmi.f32.f32 	%f58, %f57;
	sub.f32 	%f59, %f57, %f58;
	abs.f32 	%f60, %f56;
	cvt.rmi.f32.f32 	%f61, %f60;
	sub.f32 	%f62, %f60, %f61;
	ld.global.u32 	%r6, [%rd22];
	shr.u32 	%r7, %r6, 16;
	cvta.to.global.u64 	%rd31, %rd17;
	shl.b32 	%r8, %r6, 4;
	cvt.u64.u32 	%rd32, %r8;
	and.b64  	%rd33, %rd32, 1048560;
	add.s64 	%rd34, %rd31, %rd33;
	ld.global.v2.u32 	{%r9, %r10}, [%rd34];
	cvt.rn.f32.u32 	%f63, %r9;
	mul.f32 	%f64, %f59, %f63;
	cvt.rzi.u32.f32 	%r13, %f64;
	cvt.rn.f32.u32 	%f65, %r10;
	mul.f32 	%f66, %f62, %f65;
	cvt.rzi.u32.f32 	%r14, %f66;
	mad.lo.s32 	%r15, %r9, %r14, %r13;
	cvt.u64.u32 	%rd35, %r15;
	ld.global.u64 	%rd36, [%rd34+8];
	add.s64 	%rd37, %rd36, %rd35;
	ld.u8 	%r16, [%rd37];
	and.b32  	%r17, %r7, %r16;
	setp.eq.s32 	%p6, %r17, 0;
	selp.f32 	%f113, 0f00000000, 0f3F800000, %p6;

$L__BB0_4:
	cvt.u32.u64 	%r18, %rd1;
	ld.const.u64 	%rd38, [params];
	cvta.to.global.u64 	%rd4, %rd38;
	mul.wide.s32 	%rd39, %r18, 32;
	add.s64 	%rd40, %rd4, %rd39;
	add.s64 	%rd5, %rd40, 24;
	ld.global.v2.f32 	{%f120, %f69}, [%rd40+24];
	setp.geu.f32 	%p7, %f120, 0f00000000;
	ld.const.u32 	%r19, [params+340];
	setp.ne.s32 	%p8, %r19, 0;
	or.pred  	%p9, %p7, %p8;
	@%p9 bra 	$L__BB0_7;

	div.rn.f32 	%f70, %f120, 0f41200000;
	cvt.rzi.s32.f32 	%r20, %f70;
	neg.s32 	%r21, %r20;
	ld.const.u64 	%rd41, [params+224];
	cvta.to.global.u64 	%rd42, %rd41;
	mul.wide.s32 	%rd43, %r21, 16;
	add.s64 	%rd44, %rd42, %rd43;
	ld.global.f32 	%f71, [%rd44+8];
	setp.geu.f32 	%p10, %f71, 0f00000000;
	@%p10 bra 	$L__BB0_7;

	mov.f32 	%f113, 0f00000000;

$L__BB0_7:
	cvt.u32.u64 	%r22, %rd2;
	mul.wide.s32 	%rd45, %r22, 32;
	add.s64 	%rd46, %rd4, %rd45;
	add.s64 	%rd6, %rd46, 24;
	cvt.u32.u64 	%r23, %rd3;
	mul.wide.s32 	%rd47, %r23, 32;
	add.s64 	%rd48, %rd4, %rd47;
	add.s64 	%rd7, %rd48, 24;
	setp.lt.f32 	%p11, %f69, 0f00000000;
	@%p11 bra 	$L__BB0_9;
	bra.uni 	$L__BB0_8;

$L__BB0_9:
	add.f32 	%f121, %f69, 0f3F800000;
	mov.f32 	%f87, 0f3F800000;
	sub.f32 	%f88, %f87, %f28;
	sub.f32 	%f114, %f88, %f29;
	bra.uni 	$L__BB0_10;

$L__BB0_8:
	ld.global.v2.f32 	{%f73, %f74}, [%rd6];
	ld.global.v2.f32 	{%f75, %f76}, [%rd7];
	mov.f32 	%f78, 0f3F800000;
	sub.f32 	%f79, %f78, %f28;
	sub.f32 	%f114, %f79, %f29;
	mul.f32 	%f80, %f28, %f73;
	mul.f32 	%f82, %f28, %f74;
	fma.rn.f32 	%f83, %f114, %f120, %f80;
	fma.rn.f32 	%f84, %f114, %f69, %f82;
	fma.rn.f32 	%f120, %f29, %f75, %f83;
	fma.rn.f32 	%f121, %f29, %f76, %f84;

$L__BB0_10:
	ld.global.f32 	%f89, [%rd5+-12];
	ld.global.f32 	%f90, [%rd5+-8];
	ld.global.f32 	%f91, [%rd5+-4];
	ld.global.f32 	%f92, [%rd6+-12];
	mul.f32 	%f93, %f28, %f92;
	ld.global.f32 	%f94, [%rd6+-8];
	mul.f32 	%f95, %f28, %f94;
	ld.global.f32 	%f96, [%rd6+-4];
	mul.f32 	%f97, %f28, %f96;
	fma.rn.f32 	%f98, %f114, %f89, %f93;
	fma.rn.f32 	%f99, %f114, %f90, %f95;
	fma.rn.f32 	%f100, %f114, %f91, %f97;
	ld.global.f32 	%f101, [%rd7+-12];
	ld.global.f32 	%f102, [%rd7+-8];
	ld.global.f32 	%f103, [%rd7+-4];
	fma.rn.f32 	%f104, %f29, %f101, %f98;
	fma.rn.f32 	%f105, %f29, %f102, %f99;
	fma.rn.f32 	%f106, %f29, %f103, %f100;
	mul.f32 	%f107, %f105, %f105;
	fma.rn.f32 	%f108, %f104, %f104, %f107;
	fma.rn.f32 	%f109, %f106, %f106, %f108;
	sqrt.rn.f32 	%f110, %f109;
	rcp.rn.f32 	%f111, %f110;
	mul.f32 	%f119, %f106, %f111;
	mul.f32 	%f118, %f105, %f111;
	mul.f32 	%f117, %f104, %f111;

$L__BB0_11:
	st.param.f32 	[func_retval0+0], %f117;
	st.param.f32 	[func_retval0+4], %f118;
	st.param.f32 	[func_retval0+8], %f119;
	st.param.v4.b8 	[func_retval0+12], {%rs9, %rs10, %rs11, %rs12};
	st.param.f32 	[func_retval0+16], %f120;
	st.param.f32 	[func_retval0+20], %f121;
	st.param.f32 	[func_retval0+24], %f113;
	st.param.v4.b8 	[func_retval0+28], {%rs13, %rs14, %rs15, %rs16};
	ret;

}
	// .globl	oxMain
.visible .entry oxMain()
{
	.reg .b64 	%rd<2>;


	mov.u64 	%rd1, __direct_callable__oxMain;
	// begin inline asm
	// end inline asm
	ret;

}

